A 45nm CMOS, Low Jitter, All-Digital Delay Locked Loop with a Circuit to Dynamically Vary Phase to Achieve Fast Lock

The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessary) to keep the clocks continuously aligned to a common reference clock delay. This ensures error free data transfer between any two clock domains. A novel Digital DLL design is proposed to achieve short locking time by having a separate circuitry for fast lock in the DLL. The fast lock mechanism can be switched off and the power dissipation can be returned to normal levels after the DLL has locked. A separate fine-delay block makes the proposed DLL have ultra-low jitter after lock. The results show that the proposed DLL, implemented in 45nm CMOS technology, needs only 24 cycles to correct (i.e. to lock) for 500ps clock skew when compared to more than 38 lock cycles for a conventional DLL without the fast lock mechanism. A Monte-Carlo simulation yielded a RMS jitter and peakto-peak jitter values after lock of 5.26ps and 10.57ps respectively. Average power consumption before lock is <425μW with this number falling to <335μW after lock. The frequency of operation of the proposed DLL is 280MHz 1.63GHz and can be used for a variety of applications which require precise time intervals.